[−][src]Function core::arch::mips64::__msa_srar_h
pub unsafe fn __msa_srar_h(a: v8i16, b: v8i16) -> v8i16
This is supported on MIPS-64 and target feature
msa
only.Vector Shift Right Arithmetic Rounded
The elements in vector 'a'(eight signed 16-bit integer numbers) are shifted right arithmetic by the number of bits the elements in vector 'b' (eight signed 16-bit integer numbers) specify modulo the size of the element in bits.The most significant discarded bit is added to the shifted value (for rounding) and the result is written to vector(eight signed 16-bit integer numbers).