Function core::arch::mips64::__msa_srl_w

pub unsafe fn __msa_srl_w(a: v4i32, b: v4i32) -> v4i32

🔬 This is a nightly-only experimental API. (stdsimd #48556)

This is supported on MIPS-64 and target feature msa only.

Vector Shift Right Logical

The elements in vector 'a'(four signed 32-bit integer numbers) are shifted right logical by the number of bits the elements in vector 'b' (four signed 32-bit integer numbers) specify modulo the size of the element in bits.The result is written to vector(four signed 32-bit integer numbers).